Powerline communications (PLC) include systems for communicating data over the same medium (i.e., a wire or conductor) that is also used to transmit electric power to residences, buildings, and other premises. Once deployed, PLC systems may enable a wide array of applications, including, for example, automatic meter reading and load control (i.e., utility-type applications), automotive uses (e.g., charging electric cars), home automation (e.g., controlling appliances, lights, etc.), and/or computer networking (e.g., Internet access), to name only a few.
FIG. 1 shows the structure of a PHY data frame 100 for an Orthogonal Frequency-Division Multiplex (OFDM) physical layer (PHY) based on the IEEE 1901.2 standard including the various fields in the PHY header shown. For IEEE P1901.2, the PHY header is referred to as a frame control header (FCH). Data frame 100 includes a preamble 110, a FCH 120, a MAC header 130, a MAC (data) payload 140, and a FCS 150. Although not shown, the MAC header 130 includes a destination address field which is used by receiving nodes to determine if the frame received on the PLC channel is intended for that node or not. The FCH 120 does not include a destination address field.
The preamble 110 and FCH 120 are indicated as being ROBO mode modulation (Robust OFDM mode). ROBO modulation is considered robust in the sense that it may provide four times extra redundancy parity bits by using a repetition code and therefore the network may more reliably deliver data under severe channel conditions. FCH 120 includes fields including Phase Detection Counter (PDC) 121, Modulation type (MOD; such as 0 for ROBO; 1 for DBPSK and 2 for DQPSK) 122, Reserved (Rsrv) bits 123, delimiter type (DT) 124, frame length (FL; the PHY frame length in PHY symbols) 125, tone map (TM) 126 comprising TM [0:7] 126a, TM [8:15] 126b, TM [16:23] 126c, and TM [24:31] 126d, Frame Control Check Sequence (FCCS) 127, conv zeros (e.g., 6 zeros for convolutional encoder) 128, and Rsrv bits 129.
Since the PHY header in PLC standards, such as IEEE P1901.2 (e.g., FCH 120 in FIG. 1), does not include a destination address field, a node has to wait to decode the entire MAC header and MAC payload and the verification of the cyclic redundancy check (CRC) before knowing if it is the intended destination node (receiver) for the frame. Accordingly, the MAC header 130 is decoded only after the CRC verification is successful to determine if the frame is intended for that node or not. Moreover, known PLC specifications generally have no way to distinguish between corruption of the MAC header 130 and corruption of the MAC payload 140.